On October 26, 2023, the U.S. Court of Appeals for the Federal Circuit in Monterey Research, LLC v. STMicroelectronics, Inc.[1] affirmed a pair of final written decisions at the Patent Trial and Appeal Board (PTAB)[2] that invalidated challenged patent claims owned by Monterey Research (“Monterey”) covering an “improved Static Random Access Memory (SRAM) cell design and method of manufacture”[3] for computer memory.

U.S. Patent No. 6,534,805 (“U.S. Pat. No. ’805”)

Monterey’s U.S. Pat. No. ’805 protects a memory cell having multiple layers of circuit components.[4]  A conventional semiconductor memory device stores information digitally, in the form of bits (e.g., binary digits).  The memory is typically organized as a matrix of memory cells, each of which is capable of storing one bit.  The cells of the memory matrix are accessed by wordlines (that are typically associated with the rows of the memory matrix) and bitlines (that are typically associated with the columns of the memory matrix).[5]  Figure 3 of U.S. Pat. No. ’805 depicts local interconnects that correspond to bitlines (38 and 39) or a global wordline (43 and 44), each of which is associated with a single contact region (15c, 16c, 17c1, and 17c4) within the circuit.[6]

Inter Partes Review

Petitions for Inter Partes Review of U.S. Pat. No. ’805 were brought by Advanced Micro Devices, Inc. and STMicroelectronics, Inc.[7] and by Qualcomm Inc., Advanced Micro Devices, Inc., and STMicroelectronics, Inc.[8]  The dispute concerned, inter alia, claim 8, which reads:

8. A memory cell comprising a plurality of substantially oblong active regions formed in a semiconductor substrate and arranged substantially in parallel with one another, and a plurality of substantially oblong local interconnects above said substrate that extend only partially across the memory cell and are arranged substantially in parallel with one another and substantially perpendicular to said active regions.

Petitioners argued that neither the claim language nor the Specification supported Patent Owner’s proposed claim construction that a single local interconnect layer required lateral routing of signals along the interconnect layer because the word “routing” wasn’t present in the application, and Figure 3 did not illustrate any routing along the local interconnect layer, let alone specific positions that would demonstrate routing.[9]

To oppose Petitioners’ assertion, Patent Owner Monterey referenced the underlying prosecution history to support its position that the disputed limitation was limited to the embodiment in Figure 3 showing the type of lateral routing of signals being discussed.  Specifically, Monterey argued that the limitation “single local interconnect layer comprising local interconnects corresponding to bitlines and a global wordline” was added to claim 8 during reexamination to distinguish over a cited prior art reference.[10]

The PTAB found that neither the specification nor the prosecution history limited the claim scope to lateral routing[11] because Figure 3 only showed a single contact point on each relevant interconnect, rather than contacts on both ends that would impose lateral routing, and the underlying prosecution history did not disclaim any specific routing.[12]  The challenged claims were found unpatentable as obvious[13] and Monterey appealed.[14]

Federal Circuit

On appeal, the Federal Circuit affirmed the PTAB’s conclusion that Monterey’s representations made during prosecution did not restrict the claim limitation to lateral routing because those statements did not require that the local interconnects provide connections between “laterally displaced” components such that signals would have to be horizontally routed.[15]  Even if the disputed “single local interconnect layer” claim term were limited to Figure 3, the majority held that Figure 3 did not restrict the claim as argued by Monterey because Figure 3 only depicts a single contact region for each of the relevant local interconnects required by the disputed limitations,[16] leaving it ambiguous as to whether the second contact region associated with the local interconnects (about which Figure 3 is silent) required lateral and not vertical routing.  As such, the Federal Circuit agreed with the PTAB’s claim construction.

Interestingly, in dissenting in part, Judge Dyk disagreed with the majority’s holding that Figure 3 was not limited to the lateral routing construction because the PTAB concluded that “the embodiment shown in Figure 3 of the ’805 patent illustrate[d] routing . . . signals along an interconnect layer to connect laterally displaced bitlines and wordlines.”[17]  Thus, according to Judge Dyk, the PTAB determined that the rest of the claim language and specification did not limit the claim scope to the embodiment disclosed by Figure 3, not that Figure 3 was so limited.[18]  Therefore, under the PTAB’s determination, limiting the scope of the disputed claim term to the embodiment in Figure 3 would limit the claim’s scope to an embodiment connecting laterally displaced components.[19]

Practical Tips for Prosecution

Typically, to maintain flexibility for a broad claim construction, patent practitioners seek to put fewer statements and declarations on the record during prosecution.  Patent practitioners may engage in a balancing act and apply a minimalistic approach, placing just enough on the record to support the Applicant’s position, while not placing too much on the record to result in unintentional repudiations of claim scope.  However, this decision emphasizes how this approach may have unintended consequences during post-grant proceedings.

Patent practitioners should consider pursuing claims of varying scope during prosecution to protect diverse embodiments of the invention as an alternative to narrowing the claims during prosecution, which could create estoppel issues when attempting to argue for broader claim construction in post-grant proceedings at the PTAB or during litigation.

References

[1] Monterey Research, LLC v. STMicroelectronics, Inc., No. 2022-1411, 2022-1770 (Fed. Cir. 2023) (“Fed. Cir. Decision”).

[2] Advanced Micro Devices, Inc. and STMicroelectronics, Inc. v. Monterey Research, LLC, IPR2020-00990, 2021 WL 6339618 (P.T.A.B. Nov. 23, 2021) (“0990 Decision”); Qualcomm Inc. v. Monterey Research, LLC, No. IPR2020-01491, 2022 WL 682743 (P.T.A.B. Mar. 4, 2022) (“1491 Decision”).

[3] U.S. Patent No. 6,534,805 (“U.S. Pat. No. ’805”), 1:7–10.

[4] See 1491 Decision, at *2.

[5] See U.S. Pat. No. ’805, 1:32–43.

[6] See id. at 11:18–21, 13:12–13, 31.

[7] See 0990 Decision, at *4 (challenging claims 8, 10, 12, 16, 18, 22, and 23 under 35 U.S.C. § 103(a) in view of U.S. Patent No. 6,417,549 (“Oh”) individually and Oh in view of R. Jacob Baker, et al., CMOS Circuit Design, Layout and Simulation (2011) (“Baker”)).

[8] See 1491 Decision, at *4–5 (challenging several claims under 35 U.S.C. § 103(a) in view of U.S. Patent Nos. 6,347,062, 5,702,982, 5,930,163, Oh, and/or Baker).

[9] See 1491 Decision, at *17.

[10] See id. at *7 and *17.

[11] See id. at *8 (“although Figure 3 shows bitline signals can be routed horizontally . . . neither the Specification nor the claims require such routing.”).

[12] See id. at *8.

[13] See id. at *80–81. See also 0990 Decision, at *45.

[14] See Fed. Cir. Decision, at *5.

[15] See id. at *18.

[16] See id.

[17] See id. at *3 (quoting 1491 Decision, at *17) (Dyk, J., dissenting in part, concurring in part).

[18] See id. at *3.

[19] See id. at *3 and *4.

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